A base-4 leading zero detector (LZD) design is proposed in this paper. The design is similar to the approach originally proposed by V.G. Oklobdzija with a different technique. The circuit modules used in the base-4 LZD approach are designed and several N-bit LZD circuits are implemented with a standardcell realization in the Taiwan Semiconductor Manufacturing Company (TSMC) 0.65um CMOS process. The performance and layout area of the base-4 LZD realization is compared for implementations that contain only 4-to-1 and 2-to-1 multiplexers.